Computer systems continue to be designed to meet the two often opposing goals of increased performance and decreased power consumption (sometimes manifesting in trying to maintain a level of power consumption while increasing performance). The struggle to meet both goals becomes quite evident in the case of electronic devices such as portable computer systems (including notebook and handheld computers), networking appliances (including firewall appliances and intelligent routers), and banks of servers (including blade and telco servers), all of which employ memory systems having considerable quantities of DRAM (dynamic random access memory). As ever more uses for such electronic devices are found, there is a need for faster processors, greater quantities of memory, etc. However, as ever more uses for such devices are found, there is a need to consume lesser amounts of power to increase battery life in portable application and to allow for greater densities of electronic devices to be assembled together in centralized facilities.
This struggle has resulted in efforts to find ways to decrease the amount of power required by each of the components of such electronic devices, including memory devices. Known approaches include creating reduced power modes (commonly referred to as “sleep modes” or “hibernation modes”) for such electronic devices to enter into when not actively being used. Specifically, DRAM devices have been created with lower power modes, including what is commonly referred to in the DRAM device industry as “self refresh” mode where interactions between DRAM devices and other components are minimized. Self refresh modes entail using a minimal amount of logic built into a DRAM device to allow the DRAM device to autonomously carry out maintenance functions such as refreshing the DRAM device's memory cells.
However, such approaches to reducing DRAM device power consumption have not addressed the problem of power wasted as a result of the growing disparity in the voltage level at which the memory cells within DRAM devices must operate to acquire and preserve a charge indicating bit values within memory cells, and the ever lower voltage levels required by processors and other logic that are often coupled to DRAM devices. As a result of this disparity, inefficient I/O interface and memory controller logic designs must be employed, and opportunities to decrease power consumption and/or to increase the speeds at which memory is accessed by making use of lower voltage interfaces are lost.